package cim144.ctdp_array16_shift8_relu

import chisel3._
import chisel3.experimental._
import chisel3.util._

class config_para extends Bundle{
  val adc_range  = UInt(8.W)
  val out_shift  = UInt(8.W)
  val wise_num   = UInt(7.W)
  val bit_random = Bool()
  val isrelu     = Bool()
}

trait  SystemConfig{
  val CIM_XLEN         = 64
  val CIM_ADDR_SIZE    = 64
  val ROW_NUM          = 576
  val COL_NUM          = 128
  val PUSH_MAX_SIZE    = ROW_NUM * 8 /CIM_XLEN  //72  576 row, 1Byte/row
  val SAVE_MAX_SIZE    = COL_NUM * 8 /CIM_XLEN  //16  128 col, 1Byte/col

}
